1. Technical Field
The present invention relates to a test apparatus and a test method for testing a device under test.
2. Related Art
A test apparatus that tests a device under test, such as a semiconductor, supplies the device under test with a test signal having a prescribed test pattern and detects the value of a signal output from the device under test in response to the test signal. The test apparatus judges pass/fail of the device under test by comparing the detected value of the signal to the expected value.
Such a test apparatus includes a pattern generator. The pattern generator sequentially executes test commands included in a test command sequence, which is sequence data. The pattern generator sequentially outputs the test pattern corresponding to the executed test commands.
The pattern generator can execute a test command known as a “match command,” as shown in Patent Documents 1 and 2, for example. The match command is a branch command for detecting whether the value of the output signal from the device under test matches the expected value, and branching into different commands depending on whether the value of the output signal matches the expected value.
By executing a test command sequence that includes a match command, the test apparatus can perform the operations described below, for example.
A device under test including a PLL (Phase Locked Loop) outputs a lock signal when the PLL is in a stable state. A test apparatus testing such a device under test can use the match command to execute a process for exiting a loop on a condition that the value of the lock signal matches a prescribed value. As a result, the test apparatus can perform a function test after the PLL has achieved stable operation following the power supply being turned on.
A NAND flash memory outputs a ready/busy signal indicating whether a deleting operation or a recording operation is being performed. When such a NAND flash memory performs the deleting operation or recording operation, a test apparatus that tests the NAND flash memory can perform a subsequent test after detecting via the match command that the value of the ready/busy signal matches the expected value. As a result, the test apparatus can perform the subsequent test after it is ensured that the deleting operation or recording operation of the NAND flash memory is complete.    Patent Document 1: Japanese Patent Application Publication No. 2000-40389    Patent Document 2: Japanese Patent Application Publication No. H11-64454
When executing the match command, the test apparatus must allocate hardware in advance for detecting whether the value of the output signal matches the expected value, to each terminal that is a target of the detection by the match command. Accordingly, during execution of the test sequence, the test apparatus cannot dynamically change the terminals that are targets of the detection by the match command.
Furthermore, when testing a device under test in which three or more states are represented by a plurality of output signal values, the test apparatus should be able to branch into different commands for each of the three or more states. However, the test apparatus cannot dynamically change the terminals that are targets of the detection by the match command during execution of the test sequence, and it is extremely difficult to detect the three or more states expressed by the plurality of output signals using hardware. As a result, the test apparatus cannot change among different commands corresponding to three or more states.